課程說明及重點
高(gao)壓(ya)制(zhi)程(cheng)電(dian)子產(chan)(chan)品(pin)一(yi)般大的可靠性(xing)問題是(shi)靜(jing)電(dian)放電(dian)(ESD) 很(hen)差、閂鎖(LU)能力(li)也(ye)(ye)很(hen)差，而且(qie)模擬高(gao)壓(ya)電(dian)路輸(shu)出端口又會占很(hen)大面積(ji)，這(zhe)會影響(xiang)使其ESD能力(li)通常非(fei)常不佳(jia)。ESD)/LU破壞是(shi)影響(xiang)IC可靠性(xing)的重要因(yin)素也(ye)(ye)是(shi)延緩產(chan)(chan)品(pin)上(shang)(shang)(shang)市的主因(yin)，因(yin)此無論由制(zhi)程(cheng)上(shang)(shang)(shang)、設計上(shang)(shang)(shang)全方位(wei)的防護措施(shi)是(shi)必要的。本課程(cheng)是(shi)高(gao)壓(ya)集成IC
ESD/LU防護設計上(shang)(shang)(shang)之(zhi)實務課程(cheng)，更是(shi)各(ge)高(gao)壓(ya)集成IC產(chan)(chan)品(pin)ESD可靠度防護上(shang)(shang)(shang)熱門的技術。
本課程將從各種HV CMOS元器件、晶圓廠技術平臺、HV組件的汲極工程、高壓元器件ESD/LU能力如何測試介紹起，進而談論HV
CMOS 的各電性、可靠度缺點、晶圓廠HV ESD/LU 防護設計法則及各種ESD/LU保護策略及如何保護HV
LDMOS與HV 集成電路ESD/LU防護實際案例分析，后期許學員能對HV制程工藝及組件結構充分理解，并熟悉HV
IC靜電防護及LU免疫設計之防制意義。
授課對象
現職從事模擬IC與電子產品之RD設計、布局、制造、產品應用與品管、品保、FA相關技術人員 (對ESD/LU防護已有認識者)。
課程大綱
第一階段 :
I. High-Voltage CMOS Devices
◎ What’s an HV Technology ?
◎ How These Products Use the HV Process ?
◎ Foundry Technology Platform
II. Device Engineering for HV Devices
◎ Basic Concepts of an HV IC
◎ Well Engineerings
◎ Electrical Behaviors
III. HV ESD/LU Testing Issues
◎ How to Do an HV IC ESD Testing ?
◎ How to Do an HV IC Latch-up Testing ?
第二階段:
III. Weakness Issues in the HV CMOS Process
◎ High Resistive ESD Element Influence
◎ Intrinsic HV nMOS Reliability Problem
◎ Why ESD Level of the HV-CMOS I/O Protection Circuit
is So Bad ?
◎ How About the Occurred Failure Mode in the HV
CMOS ?
◎ HV Multi-Finger O/P nMOS Driver Protection Challenge
◎ Impact of Low-Holding-Voltage Issue in HV CMOS
Technology
IV HV ESD/LU Rules (ex: 5V/30V/40V)
◎ Foundry HV ESD Design Rules
◎ Foundry HV LU Design Rules
V. Some Strategies of ESD/LU Protection Design in
a HV CMOS Process
◎ How to Improve Low Vh ?
◎ How to Adjust Vt1 ?
◎ How to Guarantee That Vt2 >Vt1 ?
◎ How About the Single Finger Width Effect ?
◎ Which One Device Is More Better ?
◎ How About the N-Well Effect in a HV Drain Side
?
Day 3:
VI. How to Protect the HV LDMOS?
◎How to Do a Good ESD Immunity in the HV LDMOS?
◎ESD Protection Methods & Patents for the HV
LDMOS
VII. (HV ESD/LU Cases Study)
VIII. Summary
